1. Field of the Invention
The present invention relates to a multi stack packaging chip and a method of manufacturing the same, and more particularly, to a multi stack packaging chip generated by forming and packaging a circuit element on a cap wafer of a flip-chip packaged chip and a method of manufacturing the same.
2. Description of the Related Art
In general, elements performing specific functions like microstructures such as integrated chips (ICs), hybrid chips, radio frequency (RF) systems, or micro electro-mechanical systems (MEMSs) and actuators are easily broken by foreign materials or outer impacts. Thus, circuit elements must be packaged to be prevented from being broken by foreign materials or outer impacts and to be electrically connected to electronic parts, so as to have physical functions and shapes. To achieve such packaging, a packaging substrate is manufactured using an additional substrate, and then a base substrate on which a circuit element is mounted is bonded to the packaging substrate.
FIG. 1 is a cross-sectional view illustrating a conventional packaging of a wafer level. Using wire bonding and is disclosed in U.S. Pat. No. 6,376,280. For the conventional packaging, a viahole is formed in a predetermined area of a cap wafer 24, and a circuit element 14 performing a specific function is formed on a base wafer 12. A bonding pad 18 is formed so as to be electrically connected to the circuit element 14, and a pad 20 is bonded to the cap wafer 24 so as to seal the circuit element 14. Also, gaskets 22 are formed on the cap wafer 24 so as to be bonded to the pad 20, and gaskets 36 are formed so as to be bonded to the bonding pad 18.
Wire bonding is performed via the viahole to connect the circuit element 14 to an external power source. The circuit element 14 is electrically connected to the external power source via wires 30 and the bonding pad 18. However, the wire bonding deteriorates a performance of a chip due to an increase in a parasitic capacitance of the wires 30.
In the wire bonding method, the bonding pad 18 for electrically connecting the circuit element 14 to the external power source must be formed around the circuit element 14. Thus, a size of the chip is increased by a size of the bonding pad 18.
In a case where the chip is packaged using the wire bonding method, another wafer cannot be formed on the cap wafer 24 due to the wires 30. Thus, the chip may not be manufactured in a stack structure.